00 · IN THREE MINUTES
The answer in three steps
- 1Early node names tracked a physical dimension more closely than modern labels do.
- 2Today “2 nm” identifies a technology family with particular transistor structures, rules and performance targets.
- 3Density, power, speed, yield and cost must be compared separately.
01 · ONE NUMBER ONCE TRACKED A FEATURE
One number once tracked a feature
Older generations were often associated with gate length or half-pitch. As transistor geometry became three-dimensional and multiple dimensions limited performance, a single physical measurement stopped representing the whole process.
02 · THE NODE BECAME A PORTFOLIO NAME
The node became a portfolio name
Manufacturers use node labels to distinguish compatible design rules, transistor options, interconnect stacks and fabrication steps. Two companies can use similar names for processes with different densities and characteristics.
One number once tracked a feature
Older generations were often associated with gate length or half-pitch. As transistor geometry became three-dimensional and multiple dimensions limited performance, a single physical measurement stopped representing the whole process.
generation labelThe node became a portfolio name
Manufacturers use node labels to distinguish compatible design rules, transistor options, interconnect stacks and fabrication steps. Two companies can use similar names for processes with different densities and characteristics.
transistor geometryTransistors changed shape
FinFETs wrap a gate around a raised fin; gate-all-around devices surround stacked channels more completely. These structures improve electrostatic control without making every relevant dimension equal to the node label.
density + power + speedScaling has several scoreboards
Logic density counts usable cells per area, while performance and power depend on voltage, wiring and design. Memory cells, analog circuits and input/output structures scale at different rates.
yield + cost03 · TRANSISTORS CHANGED SHAPE
Transistors changed shape
FinFETs wrap a gate around a raised fin; gate-all-around devices surround stacked channels more completely. These structures improve electrostatic control without making every relevant dimension equal to the node label.
04 · SCALING HAS SEVERAL SCOREBOARDS
Scaling has several scoreboards
Logic density counts usable cells per area, while performance and power depend on voltage, wiring and design. Memory cells, analog circuits and input/output structures scale at different rates.
05 · MANUFACTURING DECIDES AVAILABILITY
Manufacturing decides availability
A process can demonstrate small features before it achieves high-volume yield. Useful comparisons therefore name the product, date, test conditions and measured metric rather than ranking chips by node label alone.
06 · SOURCES AND EVIDENCE
Sources and evidence
Claims are linked to foundational papers, standards or the primary study behind the update.
- 01International Roadmap for Devices and SystemsTECHNICAL STANDARD ↗
Supports a defined mechanism, measurement or evidence boundary in this article.
- 02N2 technologyINSTITUTIONAL REPORT ↗
Supports a defined mechanism, measurement or evidence boundary in this article.